SEMICON West 2026: Why Leadership Capacity Is Now the Constraint on Semiconductor Growth

SEMICON West 2026 showed an industry whose demand is outrunning its ability to execute, with experienced leadership the scarcest resource in the chain. 

We were both at SEMICON West, at Moscone Center in San Francisco from October 13 to 15, where SEMI framed the event around the industry reaching $1 trillion in annual revenue in 2026, about four years ahead of what forecasters expected. The WSTS calculation for the full year is higher again, at $1.655 trillion. Memory alone is expected to grow by 302%. 

One concern kept returning in the sessions we attended. Chipmakers and their customers have committed huge sums to new capacity. Few are sure they have the people to run it. 

What Did SEMICON West 2026 Reveal About AI Demand for Semiconductors?

The AI buildout explains the scale of those commitments. SIA and Deloitte put semiconductors at roughly 95% of the content value of a leading AI server rack. SemiAnalysis expects memory alone to take about 30% of hyperscaler capital spending this year. In 2023 and 2024 it was roughly 8%. 

Customers now buy a complete compute system, from logic and high-bandwidth memory (HBM) through advanced packaging, interconnect, power delivery, and cooling to the grid connection that feeds the data center. Contracts run longer and the capital bets are bigger. A slow ramp costs more. 

Where Are the Semiconductor Supply Bottlenecks Moving After HBM?

Some of those commitments have already run into hard limits. HBM and advanced packaging are the tightest points today. Kearney’s memory study puts the share of unconstrained demand being met at 60% to 70%, with new capacity arriving in 2028 at the earliest and substantial relief unlikely before 2030. 

Mature nodes are where the next shortage is building, as demand from 800V AI racks and physical AI starts to compete with automotive customers for power ICs, MOSFETs, microcontrollers, and other mature-node parts. 

Packaging, the other tight point, showed up almost everywhere on the technical program. Chiplets, plus 2.5D and 3D stacking, have turned the package into a source of system performance. Package design and thermal management are now central to product planning. TEL and AMD both treated packaging as where the next performance gains come from. Intel Foundry showed EMIB-T and co-packaged optics, while process engineers spent much of their time on wafer-bow control, non-destructive inspection of stacked dies, hybrid bonding, and panel-level packaging. 

Materials suppliers carry risk of their own. Helium and bromine supplies are vulnerable to disruption in the Middle East. The chemistry for the next node is not settled. Qnity’s PFAS-free resists were one answer on show. 

Industrial Policy and Export Controls Are Redrawing the Semiconductor Map

Location is now a board decision. Policy comes attached to every site. North America is rebuilding leading-edge manufacturing and packaging, helped by a US advanced manufacturing investment tax credit of 35%. Europe is backing power devices and specialty semiconductors, along with the equipment makers that serve them. Southeast Asia is moving up from assembly and test into design and advanced packaging. 

Export controls are closing markets from the other side. ASML’s China share fell to 33% of sales in 2025, and its CFO expects about 20% this year. A 2nm fab module costs between $25 billion and $35 billion to build and equip. A company that commits to a site signs up for a decade of operating decisions there, and for finding the leaders to make them. 

How Is AI Changing Semiconductor Design and Manufacturing?

AI is starting to change how chips get made, though progress is uneven. McKinsey puts the gain from automated post-downtime checks at about 30% less machine downtime, or roughly 15 hours per failure event. ThirdAI’s keynote described a fab deployment that cut false alarms from 30% to 1.6%. 

Company-wide results are harder to find. McKinsey’s latest State of AI survey puts AI high performers at about 6% of all respondents. Those are the ones attributing an EBIT impact of 5% or more to AI use. A single pilot proves little. Lifting output across a network of sites is the hard part. That takes operations leaders whom process engineers trust and who are at ease with data systems. 

AI models turn over every three to six months, while a new chip still takes two to three years. McKinsey’s session on compressing time to silicon argued that AI agents can close part of that distance, but manufacturing has hardly compressed at all, so time saved in design only helps when fab capacity is ready. 

Energy and Water Are Now Limits on Semiconductor Production

Power and water came up in almost every keynote. Average rack load has gone from about 6 kW in 2016 to 26 kW this year. Some designs now target 1 MW. AMD’s keynote treated grid capacity and data-center space as firm ceilings, and the company has set a target of a 20x gain in rack-scale energy efficiency for AI training and inference by 2030, measured against a 2024 baseline. So far it reports 4x. 

Skilled trades are the other brake. The Associated Builders and Contractors calls them a constraint, and a shortage of electricians is already pushing out data-center build schedules. Energy and water belong in the production plan now. Resource productivity will be judged alongside cost. 

Why Is Leadership Capacity the Constraint on Semiconductor Growth?

Every one of those limits has an executive’s name attached to it. During his keynote, NY CREATES’ chief human resource officer, William Bronner, said the money for the buildout is committed while the workforce behind it is not. 

A 2026 McKinsey analysis with the SEMI Foundation and the National Network for Microelectronics Education projects about 189,000 incremental roles in US semiconductors between 2026 and 2030. About 74% of them are manufacturing-related. The shortfall could reach 127,000 to 157,000 people by 2030. At SEMICON West, McKinsey’s session on the talent equation framed this as a mismatch as much as a shortage. In the same analysis, 67% of industry professionals said technology change significantly affects hiring needs. 

At the top, the numbers are far smaller. The pool is tiny. Only a few hundred executives worldwide have ramped a complex fab at volume. Fab ramps rarely fail on technology alone, since a project that is fully funded and technically sound can still miss its business case because leadership, supplier readiness, yield learning, or workforce capability arrived late. Semiconductor companies plan tools and facilities years ahead. Leadership needs the same lead time. 

Which Semiconductor Executive Profiles Are Hardest to Find?

Those few hundred people are not interchangeable. We made a related point in our paper on the post-Moore semiconductor C-suite. CFO and CHRO roles have moved furthest from their old job descriptions. Five profiles kept coming up at SEMICON West. 

• Scale leaders. These executives have ramped complex manufacturing at volume, stabilized yield, built teams across sites, and made trade-offs under capital and customer pressure. Repeatable ramp experience carries exceptional value. 
• Systems thinkers. CTOs, chief architects, operations heads, and supply-chain leaders need to understand how logic, HBM, packaging, power, and thermal performance depend on one another. The job is to allocate scarce capacity across them rather than optimize one function. 
• Geopolitically fluent CEOs and government-affairs leaders. They judge policy risk across borders and run joint programs with hyperscalers, foundries, OSATs, and key suppliers. 
• Digital manufacturing leaders. The next operations head needs credibility with process engineers. Comfort with AI-enabled manufacturing, data systems, advanced inspection, and automation counts as much. New technology has to show up in the yield numbers. 
• Talent architects. CHROs own global pipelines, mobility, succession, and retention. Our regional semiconductor research found talent to be the binding limit in every market we studied, and first-line leaders and ownership culture count for a lot in holding on to it. Brewer Science, itself employee-owned, made that case at SEMICON West. Rutgers and Aspen Institute research puts annual voluntary turnover at about 2% where broad-based employee ownership comes with a supportive culture, down from about 13%. 

How Should Semiconductor Boards Plan Executive Succession for 2027 to 2030? 

With profiles this thin, hiring must begin before a role opens. The leaders who will run this industry in 2030 are being hired over roughly the next 24 months, and boards that wait for a resignation or a new fab announcement will chase the same small group of candidates as everyone else who waited. Here is where we would start. 

• Map the 10 to 15 roles that can speed up or delay each major capacity or technology bet. Include new-country entries. 
• Use executive assessment to measure incumbents against the next operating model, not yesterday’s specification. Look at scale, systems integration, geopolitical judgment, and AI fluency. 
• Build global successor slates for fab operations, packaging, memory, process integration, and supply chain before those roles open, benchmarked against the talent pools in Taiwan and Korea as part of succession planning. 
• Create conversion pathways from adjacent manufacturing sectors such as automotive, aerospace, pharma, and defense. Process control and capital-project discipline carry over well. 
• Treat attraction, executive onboarding, retention, and knowledge transfer as one system. That counts double in emerging clusters, where scarce leaders arrive from outside. 

About the Authors

Sundar Rajan Ramalingam is a Partner at Stanton Chase with nearly three decades of global leadership experience across manufacturing and technology sectors. He has led large-scale engineering capabilities and played a key role in building and scaling global capability centers, supporting complex, multi-country operations. With a background that spans strategic HR leadership and full P&L ownership, Sundar brings a practical understanding of how talent and operations intersect in engineering-led industries, including those within the broader semiconductor ecosystem. His work focuses on helping organizations build strong executive teams, strengthen global delivery models, and align leadership with evolving business and technology priorities.   

David Harap is a Managing Director at Stanton Chase Austin, bringing over 25 years of executive search experience to his role. He has successfully placed hundreds of senior executives and functional leaders across various industries. A Cornell University graduate and Father Kelly Scholar, David lectures at the University of Texas at Austin. He is a certified Ambassador for Hofstede Insights, bringing unique insights on organizational culture to his work.