Semiconductor Spotlight: Market Dynamics and Executive Leadership Imperatives in North America

The hardest part of bringing semiconductor manufacturing back to North America was never going to be the fabs. 

The harder gap behind the CHIPS Act build sits above the technician layer where most coverage stays. The senior executive cohort needed to run the new fabs (executives with 15 to 25 years of semiconductor operating experience, ready for fab GM, operations VP, country manager, or senior technical program roles) is materially smaller in North America than the industry needs. The early 2000s saw US engineering talent flow disproportionately into software and consumer internet rather than hardware, with the US semiconductor workforce dropping 43% from its 2000 peak. Two decades later, that diversion is why a 4nm or 2nm operation in Phoenix is flying senior engineers in from Hsinchu on rotation while its competitors in Taipei can promote internally from a bench three names long. 

The policy environment around all of this hardened in 2025. The Trump administration converted $5.7 billion in remaining CHIPS Act grants and $3.2 billion from the Secure Enclave program into a 9.9% federal equity stake in Intel worth $8.9 billion in August. NVIDIA followed with a $5 billion direct investment in Intel in September. The investment tax credit for US fab construction was raised from 25% to 35% under the One Big Beautiful Bill Act. What remains in question is who runs all of it. 

Three Pressures Behind Every Regional Build

Three pressures complicate every regional build. US export controls have already proven they can redraw market access overnight, with ASML’s China revenue projected to drop from 33% of net system sales in 2025 to roughly 20% of total sales in 2026 as restrictions tighten, and the MATCH Act now in front of Congress proposes extraterritorial controls if allies do not match US policy on equipment exports. Those measures pull commercial and government affairs requirements further into senior fab management roles than they have ever been before. 

Memory is the second pressure, having moved from cyclical commodity to the AI accelerator’s binding constraint. Samsung, SK Hynix, and Micron control over 90% of global DRAM production, and SK Hynix’s 2026 HBM, DRAM, and NAND capacity is already reported as sold out, which raises the premium on senior memory operations leaders in Boise and Clay specifically. 

Back-end concentration is the third pressure, with Taiwan, China, Malaysia, and South Korea still hosting the majority of advanced packaging and testing capacity. The largest US OSAT investment, Amkor’s Peoria campus, does not come online until 2028, which means North American advanced packaging leadership has to be hired and trained before there is a domestic operational base to grow it from internally. 

Where North American Semiconductor Capital Is Flowing

North American semiconductor capital in 2026 concentrates across five categories, each with its own geography and its own executive demand profile. 

Leading-edge logic is the largest category. Global Logic & Micro fab equipment investment is projected at $228 billion over 2027 to 2029, more than any other segment. TSMC anchors it on the foundry side in Arizona, Intel anchors it on the IDM side across Arizona, Oregon, and Ohio, and Samsung anchors the third operating model in central Texas. The executive search profile each company needs differs fundamentally. 

Memory is the second category, almost entirely Micron, with capacity going up in New York and Idaho on parallel tracks that target the AI accelerator demand cycle from two different timelines. Micron’s 2026 capex of $13.5 billion is up 23% year over year, the steepest year-over-year increase among the three major DRAM suppliers. 

Foundational and analog manufacturing is the third category. Texas Instruments anchors US-domestic capacity in the segment across its Sherman, Richardson, and Lehi sites, and is one of five analog players holding 57.7% of the global market. 

Advanced packaging and equipment R&D make up the fourth category. The first US OSAT capacity at scale is going up in Arizona, with Silicon Valley anchoring equipment R&D. The National Semiconductor Technology Center has three flagship facilities: an EUV lithography hub in Albany, a design and collaboration facility in California, and an advanced packaging piloting facility in Arizona. 

Canada and Mexico make up the fifth category through US-Mexico-Canada semiconductor cooperation. Canada brings specialty manufacturing capability in compound semiconductors, photonics, and quantum computing. Mexico targets chip design and assembly, test, and packaging that complements US front-end manufacturing rather than competing with it. The North American semiconductor region in 2026 is a continental build, and the executive talent needed to run it sits across all three countries. 

North America Semiconductor Market: State-by-State Analysis

Arizona: The Phoenix Cluster and Advanced Packaging Anchor

Arizona has become the densest semiconductor cluster in the United States. TSMC, Intel, Amkor, Applied Materials, and ASML all operate or expand within roughly 30 miles of each other in metropolitan Phoenix. TSMC’s first Arizona fab is running 4nm production at Taiwan-comparable yields, its second is undergoing equipment installation for 3nm and 2nm production, and a third Phoenix fab targeting 2nm production by the end of the decade is part of $6.6 billion in CHIPS funding finalized for TSMC’s Arizona expansion. Intel’s Fab 52 in Chandler reached high-volume 18A manufacturing in early 2026, producing Core Ultra Series 3 client processors and Clearwater Forest server chips. 18A yields are reported in the 60% range and expected to reach industry-standard levels by 2027. 

What makes Arizona singular among US states is a geographic concentration no other state can match. The same metropolitan area now houses a TSMC fab producing chips that Apple and NVIDIA designed in California, an Amkor advanced packaging campus under construction across town to package those same chips for the same customers, and an Intel foundry now open to third-party clients. For the first time in decades, a US-headquartered design house can take a chip from concept to packaged module without leaving the country.  

Senior fab and packaging executives for Arizona’s footprint are scarce everywhere. Executives with proven records leading high-volume fab ramps predominantly sit in Taiwan, South Korea, and Japan. The broader Arizona ecosystem is recruiting for module integration leaders, packaging engineers, and operations executives who can run cleanroom production at the volumes the AI demand cycle requires. Companies that have built international relocation infrastructure and compensation packages competitive with Taiwan and South Korea are filling roles faster than those still calibrating to US-domestic semiconductor compensation norms from a decade ago. 

Texas: From Sherman to Austin and Taylor

Texas runs a different play than Arizona, and that distinction impacts executive search. Where Arizona is concentrated in leading-edge logic and advanced packaging, Texas is anchored by TI’s $60 billion investment in analog and embedded processing on one end and Samsung’s Taylor 2nm logic operation on the other. TI’s first 300mm fab in Sherman, SM1, began production in December 2025, with SM2’s shell complete and SM3 and SM4 in planning. Each new 300mm fab is on track to produce tens of millions of analog and embedded chips daily by the end of the decade, on top of continued production at Richardson and Lehi. Apple, Ford, Medtronic, NVIDIA, and SpaceX are the anchor customers, with SpaceX using TI’s 300mm SiGe process from Sherman in its Starlink satellite internet service, which puts US-made analog silicon directly into the AI and connectivity infrastructure stack. 

Samsung’s Taylor facility is over 90% complete by construction and skipping 4nm entirely to focus on 2nm gate-all-around production, with risk production targeted for late 2026 and Tesla’s next-generation Full Self-Driving chips reportedly the primary demand driver. Construction was halted in 2024 because of softer demand and resumed mid-2025 once the AI cycle picked up. The investment was downsized to $37 billion from the original $44 billion plan, with corresponding adjustments to CHIPS Act funding. Texas also passed its own state-level CHIPS Act in 2023, allocating $698 million for new semiconductor projects and $660 million for advanced research, alongside establishing the Texas Semiconductor Innovation Consortium. Companies expanding in Texas can stack federal and state support in ways most other US states cannot match. 

Texas executive search has a different shape from Arizona’s. Analog and embedded processing require process knowledge that is older, more cumulative, and concentrated in fewer companies. Austin’s existing chip design community (NXP, AMD, NVIDIA) offers some adjacent recruiting ground, but the executives who can bridge a Korean operating culture into US manufacturing realities are a specific profile that very few companies have ready to deploy. 

Oregon: Intel D1X, High-NA EUV, and the Process Development Anchor

Oregon’s role in the North American semiconductor industry is less visible than Arizona’s but arguably more consequential for the long-term technology pipeline. Intel’s D1X campus in Hillsboro is where the company develops every new process node before it moves to high-volume manufacturing elsewhere. The site now hosts Intel’s first High-NA EUV scanners, which the company will use to enable the 14A node for future high-volume manufacturing. Intel ran its first 18A lot at D1X before transferring the process to Fab 52 in Arizona. The same Hillsboro infrastructure now hosts 14A node enablement work that will eventually move to Ohio when those fabs come online. 

For executive search, Oregon supplies the senior process development talent the rest of US semiconductor manufacturing draws from. Process integration leaders, lithography specialists, and yield engineering executives who have lived through multiple node transitions at D1X are among the most sought-after profiles in the industry. Intel’s own retention of that talent is being tested by the same compensation pressure every other US semiconductor employer faces. Oregon’s broader tech ecosystem makes recruiting more competitive than the size of the semiconductor cluster alone would suggest, with major Nike and HP campuses pulling adjacent engineering talent and Portland’s software economy offering alternative paths for engineers who might otherwise stay in semiconductors. 

Ohio: The Silicon Heartland on a Longer Timeline

Intel’s Ohio project, announced in 2022 as the most ambitious industrial development in US history, has been pushed back repeatedly. The Licking County complex has been pushed to a 2030 production start for its first two fabs, with the shells now complete and serving as a build-ready reserve for whichever advanced node Intel determines warrants the capacity by late this decade. What’s worth watching from Ohio in 2026 is the hiring pattern. Bechtel posting new construction jobs at the site in early 2026 suggests Intel is preparing the operation for the 14A node, which would make Ohio the first US site outside Hillsboro to run a node enabled by ASML’s High-NA EUV scanners at scale. 

Ohio’s executive search problem is unusual. The state had no semiconductor manufacturing footprint before Intel arrived and very little senior technical talent on the ground, which means every fab general manager, process integration lead, and operations executive is going to be relocated in from elsewhere. That works in Intel’s favor in one respect, since candidates moving to Ohio do not face the same cost-of-living pressure they would in Phoenix, Austin, or Silicon Valley, but it works against the state in another, since building a community of senior leaders who will stay long enough to see the project through its full build-out requires Intel to deliver on a timeline that has already slipped multiple times. Companies hiring senior technical leadership for Ohio today are asking executives to bet their next decade on Intel’s foundry strategy paying off. 

New York: Micron, GlobalFoundries, and the Memory and Mature-Node Cluster

New York’s semiconductor footprint sits in two clusters that operate at very different speeds. Micron’s $100 billion four-fab DRAM campus in Clay, north of Syracuse, broke ground in January 2026 in what Governor Kathy Hochul called the largest private investment in NY history. The first fab is not scheduled to reach production until 2030. The company has reallocated $1.2 billion to Idaho from its New York CHIPS Act grant and brought forward work there, which is the practical answer to the AI memory cycle. Idaho will deliver HBM and DRAM capacity faster than New York can be built, and Micron needs both. The Clay project remains central to Micron’s 40% US-made DRAM target, but the timeline now runs through 2041 for full build-out across all four fabs. 

GlobalFoundries’ Malta campus near Albany operates on an entirely different cycle. The site has been running mature-node specialty manufacturing for years and continues to expand for automotive, industrial, and aerospace markets where the front-end nodes Intel and TSMC are racing toward are simply not relevant. Albany’s NY CREATES facility houses the National Semiconductor Technology Center’s lithography research hub, which gives the region a research anchor comparable to imec in Belgium and a recruiting story other US states have struggled to match. 

Recruiting for the two New York clusters splits along the same line. Micron’s Clay project requires large-scale industrial construction and ramp leadership of a kind the US has not needed for fab projects of this scale since the 1990s. GlobalFoundries Malta and the Albany NSTC need a different profile, namely senior process integration and specialty manufacturing leaders who can balance defense, aerospace, and automotive customer requirements at lower volumes but higher complexity per part. The two profiles rarely overlap, and companies looking at New York that confuse them tend to fill roles with the wrong people. 

Idaho and Utah: Memory, Analog, and the Mountain West Build-Out

The Mountain West is the practical answer to the AI memory cycle and the foundational-node analog buildout. Micron is expanding its Boise campus by $30 billion with CHIPS Act support, and the fast-tracked ID2 facility brings forward the company’s HBM and advanced packaging capacity that the AI accelerator market needs now rather than at the end of the decade. Idaho is the only US state outside the leading-edge logic clusters where domestic memory production is going to scale materially in the near future. That makes it the relevant location for any North American operation depending on US-made HBM or DDR5. 

Utah’s profile is anchored by Texas Instruments. LFAB1 is ramping and LFAB2 is under construction, with TI’s original $11 billion Lehi commitment representing the largest economic investment in Utah’s history. Once complete, the two fabs will run as a single connected production environment producing 28nm to 65nm analog and embedded processing nodes that go into nearly every electronic system, from automotive electrification to data center power management. NIST has provisionally allocated up to $1.61 billion in CHIPS funding for the Lehi and Sherman expansions together, alongside an estimated $6 to 8 billion in investment tax credits. 

Idaho and Utah share an executive search challenge different from the issues facing Arizona, Texas, and Oregon. Both states have small senior semiconductor talent pools relative to the scale of operations now being built. Relocation conversations for senior executives depend more heavily on lifestyle and cost-of-living arguments than on cluster density. TI’s longstanding presence in both states gives it a meaningful recruiting advantage for senior leadership that any other entrant will need years to close. 

California: Design, AI, and the Equipment R&D Anchor

California remains the most consequential US state for semiconductors despite having no major front-end fabs of the kind being built in Arizona or Texas. The state houses NVIDIA, AMD, Broadcom, Marvell, Qualcomm’s central design operations, Apple Silicon, and the headquarters of Lam Research, Applied Materials, KLA, and the major EDA firms Cadence and Synopsys. Applied Materials’ EPIC Center in Sunnyvale, the largest-ever US investment in advanced semiconductor equipment R&D and on track to open in 2026, signals where US semiconductor equipment innovation will anchor regardless of where front-end manufacturing relocates. Samsung, TSMC, and SK Hynix have all signed long-term R&D partnerships at the facility in 2026. 

California is also where the silicon photonics and AI accelerator companies driving the next phase of demand are concentrated. NVIDIA’s $4 billion combined investment in Coherent and Lumentum announced in March 2026 reflects how seriously the AI infrastructure layer now treats optical interconnects. NVIDIA Spectrum-X and Quantum-X co-packaged optics platforms launched in 2025 are pulling demand for silicon photonics manufacturing capacity faster than the supply base can ramp. 

What California recruits for sits where chip architecture, AI systems integration, packaging, photonics, and EDA tooling meet. These profiles do not look like the fab GM and process integration profiles dominating the rest of the country, and the people who can lead them are concentrated in a handful of companies that have themselves become recruiting targets. California also hosts most of North America’s quantum computing build-out, including PsiQuantum in Palo Alto, which is in the final validation stage of DARPA’s Quantum Benchmarking Initiative alongside Microsoft, with both companies on track to deliver utility-scale quantum computers within the decade.  

Canada: Photonics, Quantum, and Compound Semiconductors

Canada’s semiconductor industry is concentrated in research-adjacent specialty manufacturing rather than volume logic or memory, and Ottawa has built its 2025 strategy around the segments where the country already runs world-class capability. The Canadian Photonics Fabrication Centre, North America’s only end-to-end pure-play compound semiconductor facility, is being spun out of the National Research Council into a commercial entity backed by private investment, anchoring Canada’s role in the photonic chips going into AI data centers, defense systems, telecommunications, and quantum computing. The CDN $223 million FABrIC initiative, a five-year program managed by CMC Microsystems, is funding Canadian SMEs developing transceivers, integrated photonic platforms, and quantum-classical interconnects. 

Quantum is where Canada has placed its most concentrated bet. The Canadian Quantum Champions Program launched in late 2025 with CDN $334.3 million committed over five years and CDN $92 million in Phase 1 funding. The program has signed agreements with Anyon Systems, Nord Quantique, Photonic Inc., and Xanadu Quantum Technologies for up to CDN $23 million each, with each pursuing a different technical approach: Montreal-based Anyon on superconducting qubits, Sherbrooke-based Nord Quantique on superconducting qubits with bosonic error correction, Vancouver-based Photonic Inc. on optically-linked silicon spin qubits, and Toronto-based Xanadu on photonic quantum computing. Three of those four are also in DARPA’s Quantum Benchmarking Initiative, which makes Canadian quantum companies among the most cross-border integrated in the global research base. 

Canadian semiconductor and quantum companies are competing for two leadership categories that rarely overlap. The first is photonics process and packaging executives, where the relevant talent pool sits across the US-Canada border with Coherent, Lumentum, Cisco, and the small but established Canadian photonics community. The second is quantum systems architects and senior research-to-product translators, where the recruiting environment is truly global and the compensation expectations are set by US venture-backed quantum companies rather than the Canadian salary norms most domestic employers are calibrated to. Canadian companies competing on the substance of the research mission and the quality of the underlying technology are filling these roles, while those trying to compete on salary alone are losing candidates to US, UK, and European employers. 

Mexico: Plan México, Kutsari, and the ATP Opportunity

Mexico is not yet a semiconductor manufacturing economy at scale, but the country’s positioning for the next phase of North American supply chain integration has changed materially in the past 18 months. The Sheinbaum administration’s Plan México, announced in early 2025, identifies semiconductors as a priority sector and offers accelerated tax deductions of up to 76% for machinery and equipment used in electronic and semiconductor components manufacturing, alongside additional deductions for companies providing scientific and technical training. The Kutsari Project is building a National Semiconductor Design Center with hubs in Puebla, Jalisco, and Sonora, targeting domestic chip design capability by 2027 and a semiconductor fabrication facility by 2029. Jalisco, home to roughly 70% of Mexico’s semiconductor industry, opened its state-owned semiconductor design park in early 2026 with plans to develop 3,000 semiconductor design engineers and 10 design-focused startups by 2030. 

What makes Mexico relevant for North American executive search is the segment of the supply chain where the country can realistically compete. Assembly, testing, and packaging represents roughly 12% of the value added per chip and requires initial investments of $2 to $50 million per facility, both of which are achievable for Mexican operations in a way that front-end fabrication is not. The Milken Institute notes that 26% of Mexico’s graduates are in STEM fields and the country is projected to have a surplus of 278,000 STEM professionals in the coming years, an inverted version of the labor constraint every other North American semiconductor market is facing.  

Mexican semiconductor operations need executive profiles unlike anything required elsewhere in North America. Country managers running an ATP operation in Tijuana or Guadalajara have to combine manufacturing fluency (cleanroom standards, statistical process control, and automotive qualification cycles) with command of the very specific commercial and regulatory environment of US-Mexico cross-border manufacturing under USMCA. Design center leaders in Jalisco need to manage the bridge between local engineering talent at one compensation level and US headquarters expectations at another. These hybrid profiles do not yet exist in volume, and the companies that have built them through years of cross-border operations have a recruiting advantage that newer entrants will need to invest in deliberately to match. 

Why North America’s Semiconductor Leadership Gap Is Different

Across all nine of those geographies, companies hiring for senior semiconductor roles in 2026 are working from a US candidate pool too thin to fill the demand. TSMC Arizona, Samsung Taylor, and Micron Boise have all built rotational programs that bring senior engineers from Hsinchu, Hwaseong, and Singapore into the US for two-to-five-year tours. The longer-term question, of where the next generation of US-based senior semiconductor executives comes from once those rotational hires return home, remains unanswered for most of these operations. Beyond the numerical gap, the skill set companies are recruiting for is different from what dominated the industry in the 1990s, with current senior roles requiring fluency in AI-driven fab operations, advanced packaging, and supply chain integration at scale. 

North America has adjacent talent that the industry has historically underused. Automotive manufacturing, defense electronics, aerospace, and advanced industrial production all run reliability cultures, statistical process control disciplines, and capital project management practices that translate into semiconductor manufacturing with the right training overlay. The conversion pathway from a Tier-1 automotive process engineer or aerospace operations leader into a semiconductor fab role is achievable with cleanroom readiness, tool safety, and vacuum systems training. Few companies have built those programs at scale, but the ones that have, particularly in Arizona and Texas, are filling senior roles materially faster than those waiting for semiconductor-native candidates to appear. Cross-sector reskilling is the fastest available route to a workforce at the scale the current investment cycle requires. 

The Mountain West and Midwest states housing the largest greenfield projects have a related search challenge that companies sometimes underestimate. Senior executives evaluating Boise, Lehi, Clay, or Licking County weigh compensation against the credibility of long-term career propositions and the family infrastructure (schools, healthcare, and community continuity) that mature semiconductor clusters like Phoenix and Hillsboro can already offer. Those propositions move senior candidates from offer to acceptance in those regions. Compensation alone has not been enough. 

Semiconductor Executive Search in North America: Leadership as the Deciding Variable

The capital question for North American semiconductors has effectively been answered. Hundreds of billions of dollars in announced private investment, $39 billion in CHIPS Act direct funding awards, and the policy actions of 2025 have settled whether the build is happening. What has not been settled is whether the operations that result will run at the scale and yield their financial models assume, because that depends on the people running them rather than the equipment installed in them. 

Three responses to those constraints separate the companies filling roles from those that are not. The first is treating senior search as a capital allocation decision rather than a hiring problem, which means mapping executive demand against ramp timelines with the same discipline applied to equipment procurement. The second is building compensation, relocation, and career architectures that can compete internationally rather than only against domestic semiconductor employers. And the third is investing in conversion programs that bring leaders from adjacent industrial sectors into semiconductor roles with the training overlay that makes the transition viable. None of these are quick fixes, but all three are achievable inside the timeline the current build cycle requires if companies start them in 2026 rather than waiting for vacancies to force the question. Across the senior semiconductor searches Stanton Chase has run in North America in 2025 and 2026, the companies running these three responses in parallel rather than sequentially have been closing those searches materially faster. 

Building the cohort that did not enter the industry 20 years ago requires international recruiting, cross-sector conversion, and long-horizon talent planning of the kind capital project owners already apply to equipment and construction. The companies doing that work in 2026 will be the companies running the fabs in 2030. 

About the Authors

Jan-Bart Smits is a Managing Partner at Stanton Chase Amsterdam. He began his career in executive search in 1990. At Stanton Chase, he has held several leadership roles, including Chair of the Board, Global Sector Leader for Technology, and Global Sector Leader for Professional Services. He currently serves as Stanton Chase’s Global Subsector Leader for the Semiconductor industry. He holds an M.Sc. in Astrophysics from Leiden University in the Netherlands.    

David Harap is a Managing Director at Stanton Chase Austin, bringing over 25 years of executive search experience to his role. He has successfully placed hundreds of senior executives and functional leaders across various industries. A Cornell University graduate and Father Kelly Scholar, David lectures at the University of Texas at Austin. He is a certified Ambassador for Hofstede Insights, bringing unique insights on organizational culture to his work. 

Sundar Rajan Ramalingam is a Partner at Stanton Chase with nearly three decades of global leadership experience across manufacturing and technology sectors. He has led large-scale engineering capabilities and played a key role in building and scaling global capability centers, supporting complex, multi-country operations. With a background that spans strategic HR leadership and full P&L ownership, Sundar brings a practical understanding of how talent and operations intersect in engineering-led industries, including those within the broader semiconductor ecosystem. His work focuses on helping organizations build strong executive teams, strengthen global delivery models, and align leadership with evolving business and technology priorities.